June 2008 – Present (7 years 1 month)Santa Clara

Manage RF/AnalogI Division at Amlogic Inc.

Lead/Design Innovated Digital PLL (DPLL) project with smallest area at 0.1 mm^2 at TSMC 40 nm and 0.07 mm2 at TSMC 28 nm with RMS jitter around 2 ps. Two US patents are already issued for these designs

Lead High Speed SerDes projects such as HDMI TX at 3.4 GHz, eDP (embeeded Display Portat 2.7 GHZ, MIPI DPHY TX/ CPHY RX at 1 GHz, and LVDS at 1 GHz. Patent single configurable multi-PHY chip for LVDS/eDP/MiPi.

Lead/Design 10/100 MHz Ethernet PHY at TSMC 40nm CMOS process


Design 100 MSPS 10 bits ADC at TSMC 40 nm CMOS process and TSMC 28 nm process , SMIC 65 nm CMOS process

Design Low Noise Amplifier (LNA), Pre-PA (Driver for Power Amplifier), PA (Power Amplifier with output P1dB at 18 dBm) for 802. 11 N WLAN Transceiver at TSMC 40 nm CMOS process

Vice Presidnt of RF and Analog Department at MediaTek (聯發科) USA

MediaTek USA

February 2003 – May 2008 (5 years 4 months), San Jose

CEO of Hyperband Communication Inc. (HBC) from 2003 to 2005. Hyperband Ciommunication Inc. was merged into MediaTek Inc. at 2005.

Manage MediaTek Inc. US RF/Analog division

Lead 802.11 N WLAN transceiver project at TSMC 0.13 um CMOS process

Lead Bluetooth 2.0 Transceiver project at TSMC 0.13 um CMOS process

Design WiMax receiver chain including LNA, Mixer, Trans-Impedance Amplifier, Filter and Programmable Gain Amplifier at TSMC 65 nm CMOS process

Help MediaTek Inc. do Technical Dual Diligence to invest or buy start-up companies

Senior Manager

Silicon Image

February 1999 – February 2003 (4 years)  Sunnyvale, CA

V.P. of Silicon Communication Lab (SCL) from 1999 to 2000. Silicon Communication Lab Inc. was merged into Silicon Image Inc. at year 2000

Lead/Design SATA (Serial ATA) Standard 1.0/2.0 PHY portion of chip that running at 1.5GHz/3.0GHz respectively

Design 160 MSPS 8 bits ADC using TSMC 0.35 um process for LCD Panel front end chips

Design Line Locked PLL for LCD Panel