金心獎第三屆-趙介元系友

74級趙介元系友

學歷: 國立中山大學電機工程學系 74級學士

現職: Amlogic 副總

經歷:

Bio of Dr. Charlie Chao (趙介元)

Dr. Charlie Chao, currently Vice President of Amlogic Inc. since 2008 and Vice Chairman of Uniband Electronic, Inc. (UBEC) since 2005, has over 20 years of experience in managing and developing RF/Analog IC products. Dr. Charlie Chao founded UBEC in 2003 and sold UBEC’s US subsidiary (Hyperband Communication Inc.) into MediaTek Inc. in 2005.

Between 2005 and 2008, Dr. Charlie Chao, who was Vice President of MediatTek in USA for RF division, managed team and led the development in wireless related projects, such as Bluetooth EDR 2.0, WLAN, and WiMAX, for MediaTek Inc. He also acted as technical consultant for MediaTek branch in Singapore and headquarters in Taiwan at the same period for 3G related cellular projects.

Before founding UBEC in 2003, he served as technical management position in Silicon Image Inc. and successfully led SATA development from design to production from 2000 to 2003. The SATA product in Silicon Image Inc. is the first SATA product in the market for both 1.5 GHz and 3.0 GHz in 2002.

Prior to Silicon Image, he was founder and Vice President of Technology of Silicon Communication Lab., Inc. (SCL) and handled R&D development for LCD front-end analog chip development in 1999. He led the development for 160 MSPS 8 bits Nyquist Rate ADC and 1.6 GHz high-speed serial data transceiver for video related applications. In 2000, the start-up company (SCL) was merged into Silicon Image Inc.

Before founding his first start up company (SCL), Dr. Charlie Chao worked in Philips Semiconductor Wireless Group as design manager from 1996 to 1999. In Philips, he led and designed RF ICs in BICMOS and CMOS process for cellular phone applications. The circuits include: BICMOS 1.1GHz to 3.7GHz Fractional-N PLL and 7^th order elliptic GMC continuous time filter, CMOS Mixer, LO chain, and related RF circuits.

Prior to joining Philips, Dr. Chao worked 1 year with Cirrus Logic Inc. as a senior design engineer in 1995 and focus in the design of DLL and PLL. Earlier in his career in 1989, he worked with ACER Lab. Inc. in Taiwan as a design engineer where he designed Intel 82385 compatible Cache Controller.

Dr. Chao received his Ph.D. degree with majors at Microelectronics and Communication in Electrical Engineer from the University of Maryland/Colleague Park in 1995 and M.S. degree in Electronics from Nation Chiao-Tung University in Taiwan in 1987. He also received his Electrical Engineer B.S degree from National Sun-Yi Sen University (NSYSU) at 1985. He has published 5 technical papers and holds 24 US & Oversea patents for the area of RF and Analog Integrated Circuits.

Experience

Vice President of RF, Analog and VLSI Department

Amlogic Inc. (晶晨半導體)

June 2008 – Present (7 years 1 month)Santa Clara

Manage RF/AnalogI Division at Amlogic Inc.

Lead/Design Innovated Digital PLL (DPLL) project with smallest area at 0.1 mm^2 at TSMC 40 nm and 0.07 mm2 at TSMC 28 nm with RMS jitter around 2 ps. Two US patents are already issued for these designs

Lead High Speed SerDes projects such as HDMI TX at 3.4 GHz, eDP (embeeded Display Portat 2.7 GHZ, MIPI DPHY TX/ CPHY RX at 1 GHz, and LVDS at 1 GHz. Patent single configurable multi-PHY chip for LVDS/eDP/MiPi.

Lead/Design 10/100 MHz Ethernet PHY at TSMC 40nm CMOS process

Design 100 MSPS 10 bits ADC at TSMC 40 nm CMOS process and TSMC 28 nm process , SMIC 65 nm CMOS process

Design Low Noise Amplifier (LNA), Pre-PA (Driver for Power Amplifier), PA (Power Amplifier with output P1dB at 18 dBm) for 802. 11 N WLAN Transceiver at TSMC 40 nm CMOS process

Vice Presidnt of RF and Analog Department at MediaTek (聯發科) USA

MediaTek USA

February 2003 – May 2008 (5 years 4 months), San Jose

CEO of Hyperband Communication Inc. (HBC) from 2003 to 2005. Hyperband Ciommunication Inc. was merged into MediaTek Inc. at 2005.

Manage MediaTek Inc. US RF/Analog division

Lead 802.11 N WLAN transceiver project at TSMC 0.13 um CMOS process

Lead Bluetooth 2.0 Transceiver project at TSMC 0.13 um CMOS process

Design WiMax receiver chain including LNA, Mixer, Trans-Impedance Amplifier, Filter and Programmable Gain Amplifier at TSMC 65 nm CMOS process

Help MediaTek Inc. do Technical Dual Diligence to invest or buy start-up companies

Senior Manager

Silicon Image

February 1999 – February 2003 (4 years) Sunnyvale, CA

V.P. of Silicon Communication Lab (SCL) from 1999 to 2000. Silicon Communication Lab Inc. was merged into Silicon Image Inc. at year 2000

Lead/Design SATA (Serial ATA) Standard 1.0/2.0 PHY portion of chip that running at 1.5GHz/3.0GHz respectively

Design 160 MSPS 8 bits ADC using TSMC 0.35 um process for LCD Panel front end chips

Design Line Locked PLL for LCD Panel

Patents:

Display Bridge with Support for Multiple Display Interfaces

Application number: 20150097821

Abstract: Method and apparatus for a display bridge with support for multiple display interfaces are disclosed. The novel display bridge comprises a predriver configured to provide data input signals. A shared output driver is configured to receive the data input signals and provide output display signals compatible for driving MIPI-DSI, EDP, or LVDS displays. A regulator and current source is coupled to the shared output driver configured to regulate the shared output driver operating voltage and provide a current source for the shared output driver. A shared termination output coupled to the shared output driver is configured to provide termination resistance for the output display signals and termination voltage for the termination resistance.

Type: Application

Filed: May 9, 2014

Issued: April 9, 2015

Assignee: Amlogic Co., Ltd.

Inventors: Chao Shi, Chieh-Yuan Chao, Jinguo He, Xiang OuYang

Method and apparatus for Vernier ring time to digital converter with self-delay ratio calibration

Patent number: 8976053

Abstract: Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.

Type: Grant

Filed: October 4, 2013

Issued: March 10, 2015

Assignee: Amlogic Co., Ltd.

Inventors: Weicheng Zhang, Ming Shi, Wei-Hua Zou, Shu-Sun Yu, Chieh-Yuan Chao

Digital phase locked loop

Patent number: 8102197

Abstract: An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.

Type: Grant

Filed: October 28, 2010

Issued: January 24, 2012

Assignee: Amlogic Co., Ltd.

Inventors: Weicheng Zhang, Ming Shi, Wei-Hua Zou, Shu-Sun Yu, Chieh-Yuan Chao

Digital Phase Locked Loop

Application number: 20120013377

Type: Application

Filed: October 28, 2010

Issued: January 19, 2012

Assignee: AMLOGIC CO., LTD.

Inventors: Weicheng Zhang, Ming Shi, Wei-Hua Zou, Shu-Sun Yu, Chieh-Yuan Chao

Digital phase and frequency detector

Patent number: 8081013

Abstract: A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.

Type: Grant

Filed: July 13, 2010

Issued: December 20, 2011

Assignee: Amlogic Co., Ltd.

Inventors: Weicheng Zhang, Ming Shi, Wei-Hua Zou, Shu-Sun Yu, Chieh-Yuan Chao

Transceiving system and compound filter

Patent number: 7982533

Abstract: A transceiving system utilizing a shared filter module is provided. The shared filter module is selectively filtering signals in a first band in a first mode and a second band in a second mode. The first mode is a receiver mode whereas the second mode is a transmission mode. The shared filter module comprises a compound filter comprising two low pass filters and a coupling controller to manage input and output wiring of the low pass filters. When the coupling controller is enabled in the first mode, the compound filter acts as a bandpass filter. When the coupling controller is disabled, the compound filter acts as two independent low pass filters.

Type: Grant

Filed: September 11, 2007

Issued: July 19, 2011

Assignee: Mediatek USA Inc.

Inventors: Yiping Fan, Chieh-Yuan Chao

DISPLAY APPARATUS

Application number: 20090109242

Abstract: A display apparatus including a process module, a screen and an electric module is provided. The process module determines the display mode of an image according to the format of the image. The screen coupling the process module displays the image. The electric module coupling the screen and the process module adjusts the screen in the orientation in accordance with the display mode of the image. Thus, the display apparatus automatically adjusts the screen in the orientation in accordance with whether the display mode of an image is in the portrait mode or the landscape mode.

Type: Application

Filed: March 24, 2008

Issued: April 30, 2009

Inventors: Hsiao-Chang KUO, Chieh-Yuan CHAO

Receiver based method for de-spreading of spread spectrum signal

Patent number: 7424047

Abstract: A spread spectrum receiver whose de-spreading process based on transformed spreading codes is provided. Instead of de-spreading with original spreading codes, this approach de-spreads received signal with the spreading codes transformed from the original codes in order to eliminate the negative impact of system impairments such as frequency offset to a spread spectrum receiver. Before de-spreading with the transformed code, the received signal goes through the same transformation as the original codes do. After a transformation, the transformed codes may exist some undesirable property such as spreading code having DC content. An approach is given to cancel unwanted side effects relating the transformed spreading codes. The approaches are very effective for spread spectrum system based on frequency modulation scheme such as MSK.

Type: Grant

Filed: November 13, 2003

Issued: September 9, 2008

Assignee: Uniband Electronic Corp.

Inventors: Yiping Fan, Syang-Myau Hwang, Hongyu Li, Chieh-Yuan Chao

Circuits and methods for fast-settling signal alignment and DC offset removal

Patent number: 7408395

Abstract: Fast settling circuits and methods designed to align input signal amplitude level and to remove DC offset voltages with minimal loss of low frequency signal in receiving analog circuits are disclosed. With the key innovative circuits and methods for signal peak alignment, the disclosed circuits and methods achieve fast settling without significant attenuation of the input signal. Peak aligning circuits and methods can be implemented along with conventional RC AC coupling circuits. In applying the aligning circuits and methods to differential signal pair, DC offsets can be easily removed.

Type: Grant

Filed: May 1, 2003

Issued: August 5, 2008

Assignee: Hyperband Communication, Inc.

Inventors: Kanyu Cao, Yiping Fan, Hongyu Li, Chieh-Yuan Chao

Chip-to-symbol receiver despreader architectures and methods for despreading spread spectrum signals

Patent number: 7366227

Abstract: In a spread spectrum system, methods and despreader architectures for despreading the received spreaded codes with the use of a single correlator and a single correlation code is provided. Before despreading the incoming received spreaded codes, a single correlation code is generated using a symbol from a set of symbols that has been mapped into a set of differential encoded PN codes. Despreading output samples for each received spreaded code are obtained by correlating the received spreaded code with this single correlation code. Correlation is accomplished by multiplying each received sample of the received spreaded codes with the correlation code samples and accumulating the products of this multiplication. After correlation, the index for the maximum or minimum peak of the despreading output samples for each code is identified. This index can then be mapped into a symbol corresponding to the transmitted information.

Type: Grant

Filed: June 23, 2004

Issued: April 29, 2008

Assignee: Hyperband Communications, Inc.

Inventors: Syang-Myau Hwang, Yiping Fan, Chen-Yi Chang, Hongyu Li, Chieh-Yuan Chao

RF amplifier with a bias boosting scheme

Patent number: 7365604

Abstract: The present invention provides methods and apparatuses for an amplifier circuit for amplifying an input signal. An amplifier circuit for amplifying an input signal comprises an amplifying transistor circuit having a power transistor and a dc bias circuit having a plurality of current mirror circuits and a discharge transistor wherein the discharge transistor and the power transistor form a combined current mirror circuit to control quiescent current in the power transistor.

Type: Grant

Filed: December 16, 2005

Issued: April 29, 2008

Assignee: Mediatek Inc.

Inventors: Sifen Luo, Yiping Fan, Hongyu Li, Chieh-Yuan Chao

TRANSCEIVING SYSTEM AND COMPOUND FILTER

Application number: 20080002597

Type: Application

Filed: September 11, 2007

Issued: January 3, 2008

Assignee: CRYSTALMEDIA TECHNOLOGY, INC.

Inventors: Yiping Fan, Chieh-Yuan Chao

Active polyphase filter

Patent number: 7271647

Abstract: The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first resistor coupled between current legs of the first cascoded differential amplifier and the second cascoded differential amplifier having a first capacitor coupled between current legs of the second cascoded differential amplifier; and a third and fourth cascoded differential amplifiers configured to receive said first and said second differential signals, the third cascoded differential amplifier having a second resistor coupled between current legs of the third cascoded differential amplifier and the fourth cascoded differential amplifier having a second capacitor coupled between current legs of the fourth cascoded differential amplifier; wherein the first and second cascoded differential amplifiers are configured to provide a first differential outp

Type: Grant

Filed: August 22, 2005

Issued: September 18, 2007

Assignee: Mediatek, Inc.

Inventors: Kanyu Mark Cao, Yiping Fan, Hongyu Li, Chieh-Yuan Chao

RF amplifier with a bias boosting scheme

Application number: 20070139120

Type: Application

Filed: December 16, 2005

Issued: June 21, 2007

Inventors: Sifen Luo, Yiping Fan, Hongyu Li, Chieh-Yuan Chao

Active polyphase filter

Application number: 20070040604

Type: Application

Filed: August 22, 2005

Issued: February 22, 2007

Inventors: Kanyu Cao, Yiping Fan, Hongyu Li, Chieh-Yuan Chao

Shared receiver and transmitter filter

Application number: 20070040605

Abstract: The present invention provides methods and apparatuses for a shared filter transceiving system. A shared filter transceiving system having a capacitor bank to adjust the time constant of the shared filter comprises a first input configured to receive a first signal. The capacitor bank is coupled to the first input having a plurality of selectable capacitors including a reference capacitor. A second input is coupled to the capacitor bank configured to receive a second signal. A configurable switch is coupled to the capacitor bank configured to couple a first selectable capacitor with the reference capacitor when the first input is active and couple a second selectable capacitor with the second reference capacitor when the second input is active. The second selectable capacitor is a predetermined offset value of the first selectable capacitor.

Type: Application

Filed: August 22, 2005

Issued: February 22, 2007

Inventors: Yiping Fan, Chang-Yu Wang, Hongyu Li, Chieh-Yuan Chao

Voltage swing detection circuit for hot plug event or device detection via a differential link

Patent number: 7009827

Abstract: In some embodiments, a device detection circuit for detecting whether a device is coupled to a differential link, a transmitter (e.g., a transceiver) including such a circuit, and a system including such a transmitter. Preferably, the device detection circuit includes two branches (each branch including a switch), a current source that causes current to flow through either branch, or to be shared by both branches, depending on the state of each switch, and a voltage swing detector configured to detect the voltage between a node (of one branch) and a node (of the other branch) during a device detection operation. In other embodiments, the invention is a device (e.g., a receiver) including a differential termination that can be coupled to a differential link, and an electrical overstress protection circuit coupled to the termination and configured to protect the device against electrical stress during a hot plug event.

Type: Grant

Filed: October 15, 2002

Issued: March 7, 2006

Assignee: Silicon Image, Inc.

Inventors: Dongyun Lee, Chieh-Yuan Chao, Jen-Dong Yuh

Receiver based method for de-spreading of spread spectrum signal

Application number: 20050105596

Type: Application

Filed: November 13, 2003

Issued: May 19, 2005

Inventors: Yiping Fan, Syang-Myau Hwang, Hongyu Li, Chieh-Yuan Chao

Chip-to-symbol receiver despreader architechtures and methods for despreading spread spectrum signals

Application number: 20050105597

Type: Application

Filed: June 23, 2004

Issued: May 19, 2005

Inventors: Syang-Myau Hwang, Yiping Fan, Chen-Yi Chang, Hongyu Li, Chieh-Yuan Chao

CIRCUITS AND METHODS FOR FAST-SETTLING SIGNAL ALIGNMENT AND DC OFFSET REMOVAL

Application number: 20040217797

Type: Application

Filed: May 1, 2003

Issued: November 4, 2004

Inventors: Kanyu Cao, Yiping Fan, Hongyu Li, Chieh-Yuan Chao

Fast-settling DC offset removal circuits with continuous cutoff frequency switching

Patent number: 6784727

Abstract: A fast-setting DC offset removal circuit with continuous cutoff frequency switching is disclosed. In the preferred embodiment, the circuit is implemented using a pair of RC filters for receiving a differential signal pair and a continuous, variable resistance control circuit. The control circuit can be current-controlled or voltage controlled to provide fast settling of the received signal and the removal of the DC offset components. Additionally, by using a current-controlled control circuit, the cutoff frequency of the RC filter can be ramped from high to low in a continuous manner, thereby minimizing the generation of DC offsets.

Type: Grant

Filed: May 21, 2003

Issued: August 31, 2004

Assignee: Hyperband Communication, Inc.

Inventors: Kanyu Cao, Tung-Shan Chen, Hongyu Li, Chieh-Yuan Chao

Fully differential continuous-time current-mode high speed CMOS comparator

Patent number: 6535029

Abstract: A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed.

Type: Grant

Filed: May 1, 2001

Issued: March 18, 2003

Assignee: Silicon Image, Inc.

Inventors: Shou-Po Shih, Chieh-Yuan Chao, Yuming Cao, Yu-Jen Wu

Fully differential continuous-time current-mode high speed CMOS comparator

Application number: 20020186052

Type: Application

Filed: May 1, 2001

Issued: December 12, 2002

Inventors: Shou-Po Shih, Chieh-Yuan Chao, Yuming Cao, Yu-Jen Wu

Cyclic phase signal generation from a single clock source using current phase interpolation

Patent number: 6380783

Abstract: A system and corresponding method for generating multiple phases within a single clock cycle of an input signal is disclosed. The method includes the steps of generating a plurality of output signals from an input source signal, where each of the plurality of output signals represents a phase-shifted version of the input signal. Next, select a pair of signals from the plurality of output signals to act as clock signals, where the selected pair of clock signals define the operating region within which the multiple phases are bounded. Then, provide a pair of complementary weighted bias currents in response to a control signal, where each of the complementary bias currents is used to generate the multiple phases of the present invention. Thereafter, the pair of weighted bias currents presented to a node are adjusted in response to the selected pair of clock signals, where the selected pair of clock signals operates to adjust the rate of change of the weighted bias currents.

Type: Grant

Filed: October 13, 2000

Issued: April 30, 2002

Assignee: Silicon Communications Lab, Inc.

Inventors: Chieh-Yuan Chao, Yuming Cao

Papers:

1 Optimal testing of VLSI analog circuits

Chieh-Yuan Chao; Hung-Jen Lin; Miler, L.

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Year: 1997, Volume: 16, Issue: 1

Pages: 58 - 77, DOI: 10.1109/43.559332

Cited by: Papers (30)